1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device including a memory cell array of an open bit line architecture.
2. Description of Related Art
In a DRAM (Dynamic Random Access Memory), which is a representative type of semiconductor memory devices, there has been known an open bit line architecture and a folded bit line architecture as methods for connecting a pair of bit lines to a sense amplifier. The open bit line architecture is a method in which a pair of bit lines connected to one sense amplifier is wired in mutually opposite directions with the sense amplifier sandwiched therebetween. Therefore, the pair of bit lines connected to the one sense amplifier is respectively allocated to a different memory mat. On the other hand, the folded bit line architecture is a method in which a pair of bit lines connected to one sense amplifier is wired in the same direction from the sense amplifier. Therefore, the pair of bit lines connected to the one sense amplifier is allocated to a same memory mat.
The DRAM of the open bit line architecture has a characteristic such that a memory capacity of memory mats located at end portions in a bit line direction can be half of a memory capacity of other memory mats. Therefore, there is widely used a technique where address allocation is performed such that two memory mats located at the end portions are always selected simultaneously, thereby securing the same memory capacity as that when the other memory mats are selected (see Japanese Patent Application Laid-open No. 2001-135075).
Meanwhile, semiconductor memory devices such as DRAMs are occasionally designed such that an I/O number (a bit number of data that can be simultaneously input/output with respect to outside) is selectable (see Japanese Patent Application Laid-open No. H11-213697). When the open bit line architecture is employed in such DRAMs, there occur problems that selection of I/O lines becomes complicated, an area of the memory cell array increases and the like. These problems are explained below with reference to FIGS. 7 to 11. The following explanations with reference to FIGS. 7 to 11 do not represent a known prior art, but they present hypothetical examples assumed by the present inventor(s) to explain the problems mentioned above.
FIG. 7 is a first example of a DRAM of the open bit line architecture in which the I/O number can be set to 8 bits or 16 bits. The DRAM shown in FIG. 7 is a DDR2 (Double Data Rate 2) DRAM in which a prefetch number is 4 bits. Therefore, when the I/O number is set to 8 bits, data of 32 (=8×4) bits is simultaneously input/output from a memory cell array, and when the I/O number is set to 16 bits, data of 64 (=16×4) bits is simultaneously input/output from the memory cell array.
In the example shown in FIG. 7, nine memory mats MAT0 to MAT8 are arranged next to each other in that order in a Y direction, and sense amplifier arrays SA(A) to SA(H) are arranged between the memory mats that are adjacent to each other in the Y direction. Each sense amplifier array is of the open bit line architecture, and one sense amplifier array is allocated with respect to two memory mats that are adjacent to each other in the Y direction. Each sense amplifier array is connected to four pairs of main I/O wirings MIO via four pairs of local I/O wirings LIO. As a result, data of 4 bits is output/input from/in each sense amplifier array. In FIG. 7, four pairs of the local I/O wirings LIO and four pairs of the main I/O wirings MIO are shown with one solid line, respectively. With this configuration, the nine memory mats MAT0 to MAT8 arranged next to each other in the Y direction can input/output data of 16 bits simultaneously at the maximum. As shown in FIG. 7, because four columns of memory mats are arranged along an X direction, data of 64 bits in total can be input/output simultaneously.
Selection of memory mats is performed by using upper bits X11 to X13 of a row address. A 3-bit value (*, *, *) assigned to a memory mat in FIG. 7 represents the upper bits X11 to X13 of a corresponding row address. As shown in FIG. 7, the same row address with the upper bits X11 to X13=(0, 0, 0) is assigned to the memory mats MAT0 and MAT8 located at both the end portions in the Y direction; therefore, these memory mats MAT0 and MAT8 are always accessed simultaneously. A memory capacity of the memory mats MAT0 and MAT8 is half of a memory capacity of the other memory mats MAT1 to MAT7. Remaining bits X10 to X0 of the row address are supplied to a row decoder XDEC and these bits are used for selecting word lines in the selected memory mat. A column address is supplied to a column decoder YDEC and it is used for selecting a column switch that connects a sense amplifier to a local I/O wiring.
When the I/O number is set to 8 bits, one memory mat among the memory mats MAT1 to MAT7, or both the memory mats MAT0 and MAT8 are selected. As a result, data of 32 bits are simultaneously input/output by using 32 pairs of the main I/O wirings MIO. The remaining 32 pairs of the main I/O wirings MIO are not used. On the other hand, when the I/O number is set to 16 bits, twice the number of memory mats in the above case are selected by ignoring (don't care) the uppermost bit X13 of the row address. As a result, data of 64 bits are simultaneously input/output by using 64 pairs of the main I/O wirings MIO.
Assuming that a memory mat MATU (an upper side) is selected when a logical level of the uppermost bit X13 is 0, and a memory mat MATL (a lower side) is selected when the logical level of the uppermost bit X13 is 1, then it can be seen from FIG. 7 that, the sense amplifier arrays SA(D) and SA(H) are sandwiched between the memory mat MATU and the memory mat MATL. No problem arises when the uppermost bit X13 is ignored, that is, when the I/O number is set to 16 bits. However, when the uppermost bit X13 is valid, that is, when the I/O number is set to 8 bits, a connection relation between the memory mat MATU and the memory mat MATL and read/write buses changes depending on which one of the memory mat MATU and the memory mat MATL is accessed.
As a result, as shown in FIG. 8, which is an enlarged diagram, although the main I/O wiring MIO(U0) is fixedly allocated to the memory mat MATU and the main I/O wiring MIO(L0) is fixedly allocated to the memory mat MATL, because the main I/O wirings MIO(U1) and MIO(L1) are allocated to both the memory mats MATU and MATL, there arises a necessity for dynamic selection of a read/write amplifier RWAMP to be booted and switching of a connection relation between the read/write amplifier RWAMP and a read/write bus RWBS.
FIGS. 9A and 9B are tables showing a relation among the upper bits X11 to X13 of the row address and the selected memory mat and the like, where FIG. 9A represents a case where the I/O number is set to 8 bits and FIG. 9B represents a case where the I/O number is set to 16 bits.
It can be seen from FIG. 9B that, when the I/O number is set to 16 bits, control is simple because the uppermost bit X13 is ignored. In contrast, control is complicated in the case of FIG. 9A; because, when the I/O number is set to 8 bits, when the upper bits X11 to X13 of the row address are (0, 0, 0) or (0, 0, 1), the main I/O wiring MIO and the read/write amplifier RWAMP on both the upper side and the lower side are used.
FIG. 10 is a second example of a DRAM of the open bit line architecture in which it is possible to set the I/O number between 8 bit and 16 bit. The DRAM shown in FIG. 10 is also a DDR2 DRAM.
The DRAM shown in FIG. 10 differs from the DRAM shown in FIG. 7 in that, 10 pieces of the memory mats MAT0 to MAT9 are arranged in that order in the Y direction, the sense amplifier arrays SA(A) to SA(D) are arranged in between the memory mats MAT0 to MAT4 that are adjacent to each other in the Y direction, and the sense amplifier arrays SA(E) to SA(H) are arranged in between the memory mats MAT5 to MAT9 that are adjacent to each other in the Y direction. Because no memory mat is arranged between the memory mats MAT4 and MAT5, these memory mats MAT4 and MAT5 have, similarly to the memory mats MAT0 and MAT9, a memory capacity that is half of the memory capacity of the other memory mats MAT1 to MAT3 and MAT6 to MAT8. Moreover, the same row addresses X11 to X13=(0, 0, 0) are assigned to the memory mats MAT0 and MAT4; therefore, these memory mats MAT0 and MAT4 are always accessed simultaneously. Similarly, the same row addresses X11 to X13=(0, 0, 1) are assigned to the memory mats MAT5 and MAT9; therefore, these memory mats MAT5 and MAT9 are always accessed simultaneously.
In the present example, because no sense amplifier array exists sandwiched between the memory mat MATU and the memory mat MATL, as shown in FIG. 11, which is an enlarged diagram, the main I/O wirings MIO(U0) and MIO(U1) are fixedly allocated to the memory mat MATU, and the main I/O wirings MIO(L0) and MIO(L1) are fixedly allocated to the memory mat MATL.
In this configuration, because it is not necessary to switch the connection relation between the read/write amplifier RWAMP and the read/write bus RWBS, the circuit configuration and the control become simple.
In the DRAM shown in FIG. 10; however, because four memory mats that have half the memory capacity of the other memory mats are used, an overall size of the memory array increases.
As explained above, when the open bit line architecture is employed in a DRAM in which it is possible to switch I/O numbers, there are problems such that selection of I/O lines becomes complicated, or the area of the memory cell array increases. These problems are not limited to DRAMs, but can occur to other semiconductor memory devices that employ the open bit line architecture, and can also occur to all semiconductor devices that include these devices.